1. Field of the Invention
The present invention relates to a semiconductor device in which a circuit including a thin film transistor (hereinbelow, abbreviated to “TFT”) is formed on a substrate having an electrically insulating surface, and a method of fabricating the semiconductor device. By way of example, it relates to the constructions of an electrooptic device which is typified by a liquid crystal display device, and an electronic equipment in which the electrooptic device is installed. Incidentally, here in this specification, the expression semiconductor device is intended to signify general devices which function by utilizing semiconductor properties, and it shall cover within its category such electrooptic device and the electronic equipment as exemplified above.
2. Description of the Related Art
There have been positively fostered the developments of techniques for fabricating an active matrix type liquid crystal display device by providing TFTs on a glass substrate or a quartz substrate. Among the TFTs, a TFT whose active layer is a semiconductor film having a crystalline structure (hereinbelow, termed crystalline TFT) attains a high mobility. It is therefore said that the crystalline TFTs can integrate functional circuits on an identical substrate, thereby to realize image display of high definition.
Here in this specification, the semiconductor film having a crystalline structure shall cover a single-crystal semiconductor, a polycrystalline semiconductor and a microcrystalline semiconductor. Further, it shall cover semiconductors disclosed in the official gazette of a Japanese Patent Application Laid-open No. 7-130652 (1995) which corresponds to a U.S. Pat. No. 5,642,826, a Laid-open No. 8-78329 (1996), a Laid-open No. 10-135468 (1998) which corresponds to a U.S. patent application Ser. No. 08/951,193, a Laid-open No. 10-135469 (1998) which corresponds to a Ser. No. 08/951,819, or a Laid-open No. 10-247735 (1998) which corresponds to a Ser. No. 09/034,041.
In order to construct the active matrix type liquid crystal display device, the n-channel TFTs (hereinbelow, termed pixel TFTs) of a pixel matrix circuit are necessary in as large a number as 1,000,000 through 2,000,000. Further, when the TFTs of functional circuits provided around the pixel matrix circuit are added, a still larger number of crystalline TFTs are necessary. Specifications required of the liquid crystal display device are severe. For the purpose of stably presenting image display, eventually, it is the primary requisite to ensure the reliability of each individual crystalline TFT.
The characteristics of a field effect transistor such as the TFT can be considered as being divided into a linear region where a drain current and a drain voltage increase in proportion, a saturation region where the drain current becomes saturated even when the drain voltage is increased, and a cutoff region where ideally no current flows even when the drain voltage is applied. In this specification, the linear region and the saturation region shall be called an ON region of the TFT, and the cutoff region an OFF region. Besides, for the sake of convenience, the drain current in the ON region shall be called an ON current, and a current in the OFF region an OFF current.
Concerning the pixel TFT, a gate voltage having an amplitude of about 15 to 20 V is applied as a drive condition. Accordingly, the pixel TFT needs to satisfy the characteristics of both the ON region and the OFF region. On the other hand, each peripheral circuit for driving the pixel matrix circuit is constructed on the basis of a CMOS circuit, in which importance is chiefly attached to the characteristics of the ON region.
In this regard, it is said that the crystalline TFT is still inferior in point of reliability to a MOS transistor (a transistor fabricated on a single-crystal semiconductor substrate) which is used for an LSI, etc. By way of example, when the crystalline TFT is continuously driven, such deteriorating phenomena as lowering in the field effect mobility, decrease in the ON current and increase in the OFF current are sometimes observed. A cause for the deteriorating phenomena is the injection of hot carriers, that is, the hot carriers created by a high electric field near the drain of the TFT incur the deteriorating phenomena.
In the technical field of the LSIs, an LDD (Lightly Doped Drain) structure has been known as an expedient for decreasing the OFF current of the MOS transistor and for mitigating a high electric field near the drain of the MOS transistor. The structure is such that impurity regions of low concentration are provided outside a channel forming region. The low-concentration impurity regions are called LDD regions.
Even in the crystalline TFT, the formation of an LDD structure has, of course, been known. The official gazette of Japanese Patent Application Laid-open No. 7-202210 (1995), for example, discloses a technique wherein a gate electrode is formed into a structure of two layers which have widths different from each other, and concretely, in which the upper layer is narrower than the lower layer, and ions are subsequently implanted using the gate electrode as a mask, whereby LDD regions are formed by one time of ion implantation by utilizing the different penetration depths of the ions based on the fact that the thickness of the gate electrode is not uniform. Herein, the gate electrode overlaps the LDD regions directly.
Such a structure has been known as a GOLD (Gate-drain Overlapped LDD) structure, a LATID (Large-tilt-angle implanted drain) structure, or an ITLDD (Inverse T LDD) structure. It can mitigate the high electric field near the drain, thereby to prevent the phenomenon of the hot carrier injection and to enhance the reliability. In, for example, Mutsuko Hatano, Hajime Akimoto and Takeshi Sakai: IEDM97 TECHNICAL DIGEST, pp. 523-526, 1997, a TFT which has a GOLD structure based on side walls formed of silicon has been verified to attain a reliability which is far superior to those of TFTs of other structures.
However, the structure laid open in the above paper has the problem that the OFF current of the TFT increases more than with the conventional LDD structure, and it necessitates a measure for eliminating the problem. Especially in the pixel TFT constituting the pixel matrix circuit, the increase of the OFF current results in augmenting power dissipation or/and causing abnormality to appear in the image display. Therefore, the GOLD structure cannot be applied to the crystalline TFT as it is.